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K4C89183AF
288Mb x18 Network-DRAM2 Specification Version 0.7
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REV. 0.7 Jan. 2005
K4C89183AF
Revision History
Version 0.0 (Oct. 2002) - First Release Version 0.01 (Nov. 2002) - Changed die revision from D-die to F-die - Corrected typo - Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram. Version 0.1 (Apr. 2003) - Added 800Mbps(400Mhz) product - Changed operating temperature from Ta to Tc. - Changed capacitance of ADDR/CMD/CLK From Min Addr/CMD/CLK 1.5 Max 2.5 Min 1.5 To Max 3.0
- Changed tDSS(DS input Falling Edge to Clock Setup Time) From F6 CL4 CL5 CL6 CL7 0.9 0.9 0.9 FB 0.9 0.9 0.9 F5 1.0 1.0 1.0 G7 0.75 0.75 0.75 0.75 F6 0.75 0.75 0.75 To FB 0.8 0.8 0.8 F5 1.0 1.0 1.0 -
- Added CL7 for 800Mbps - Deleted TSOP package outline Version 0.11 (Apr. 2003) - Corrected typo in page 3.(Deleted bi-directional strobe) - Corrected min. Vref to VDDQ/2x95% in page 7 Version 0.2 (Aug. 2003) - Added package physical dimension - Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future) - Changed DC test condition From IDD1S,IDD2N,IDD2P,IDD5,IDD6 - Changed low frequency spec like below From Unit : ns tCK max@CL=4 tCK max@CL=5 tCK max@CL=6 F6 7.5 7.5 7.5 FB 7.5 7.5 7.5 F5 7.5 7.5 7.5 F6 6.0 6.0 6.0 To FB 6.0 6.0 6.0 F5 6.0 6.0 6.0 To IDD1S,IDD2N,IDD2P,IDD5B,IDD6 IDD4W, IDD4R Changed point Changed condition newly inserted
- Changed AC test load picture Version 0.3 (Nov. 2003) - Changed Packge type from die-exposed to full molded - Changed Package code in Partnumber
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K4C89183AF
Version 0.31 (Mar., 2004) - Corrected typo. in page 7 (Changed operating Temperature to 85'C, case temperature) Version 0.4 (Jun., 2004) - Changed from "target" to "Preliminary" - Changed min. tCK@CL5 to 3.5ns in "-F6" From F6 CL = 4 tCK Clock Cycle Time (min) CL = 5 CL = 6 Version 0.5 (Aug., 2004) - Deleted self-refresh function and BL2 from spec Version 0.51 (Aug., 2004) - Corrected error in page 54, "Package Out line Drawing". (Just 4 balls were missing in drawing) Version 0.6 (Nov., 2004) - Deleted "preliminary" - Changed current value in page 9 Version 0.7 (Jan., 2005) - Deleted the tDQSQA in page 11 - Deleted the tSSK in page 11 4.0 ns 3.33 ns 3.0ns To F6 4.0 ns 3.5 ns 3.0ns
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K4C89183AF
4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as 4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can operate fast core cycle compared with regular DDR SDRAM. K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
Parameter CL = 4 tCK Clock Cycle Time (min) tRC Random Read/Write Cycle Time (min) tRAC Random Access Time (min) IDD1S Operating Current (single bank) (max) IDD2P Power Down Current (max) CL = 5 CL = 6 K4C89183AF F6 4.0 ns 3.5 ns 3.0ns 20.0 ns 20.0 ns 320mA 70mA FB 4.5 ns 3.75 ns 3.33 ns 22.5 ns 22.5 ns 300mA 65mA F5 5.0 ns 4.5 ns 4.0 ns 25 ns 25 ns 280mA 60mA
*
*
* * * * * * * *
* * * * * *
Fully Synchronous Operation - Double Data Rate (DDR) - Data input/output are synchronized with both edges of DS / QS. - Differential Clock (CLK and CLK) inputs - CS, FN and all address input signals are sampled on the positive edge of CLK. - Output data (DQs and QS) is aligned to the crossings of CLK and CLK. Fast clock cycle time of 3.0 ns minimum - Clock : 333 MHz maximum - Data : 666 Mbps/pin maximum Quad Independent Banks operation Fast cycle and Short Latency Uni-directional Data Strobe Distributed Auto-Refresh cycle in 3.9us Power Down Mode Variable Write Length Control Write Latency = CAS Latency-1 Programable CAS Latency and Burst Length - CAS Laatency = 4, 5, 6 - Burst Length = 4 Organization : 4,194,304 words x 4 banks x 18 bits Power Supply Voltage VDD : 2.5V 0.125V VDDQ : 1.4V 1.9V 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD
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K4C89183AF
Pin Names
Pin A0 ~ A14 BA0, BA1 DQ0 ~ DQ17 CS FN PD CLK, CLK DS/QS VDD VSS VDDQ VSSQ VREF NC Name Address Input Bank Address Data Input/Output Chip Select Function Control Power Down Control Clock Input C Write/Read data strobe Power (+2.5V) Ground E Power (+1.8V) (for I/O buffer) Ground (for I/O buffer) Reference Voltage No Connection H J K L M N P R DQ9 VREF CLK A12 A11 A8 A5 VSS DS Vss CLK PD A9 A7 A6 A4 QS VDD FN CS BA1 A0 A2 A3 DQ8 A14 A13 NC BA0 A10 A1 VDD F G DQ12 DQ11 DQ10 VssQ VDDQ VssQ VDDQ VssQ VDDQ DQ5 DQ6 DQ7 D DQ14 DQ15 VDDQ DQ13 VssQ DQ4 DQ2 DQ3 B DQ16 VssQ VDDQ DQ1 A 1 Index Vss DQ17 DQ0 VDD 2 3 4 5 6
PIN ASSIGNMENT (TOP VIEW)
ball pitch=1.0 x 1.0mm x18
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K4C89183AF
Block Diagram
CLK CLK PD DLL CLOCK BUFFER
To Each Block
BANK #3 CS FN COMMAND DECODER CONTROL SIGNAL GENERATOR BANK #2 DATA CONTROL AND LATCH CIRCUIT READ DATA BUFFER WRITE DATA BUFFER DQ BUFFER DQ0 ~ DQ17 BANK #1 BANK #0
ROW DECODER
A0 ~ A14 BA0, BA1
ADDRESS BUFFER
MODE REGISTER
MEMORY CELL ARRAY
UPPER ADDRESS LATCH LOWER ADDRESS LATCH
COLUMN DECODER
REFRESH COUNTER
BURST COUNTER
WRITE ADDRESS LATCH ADDRESS COMPARATOR DS QS
Note : The K4C89183AD configuration is 4 Bank of 32768 x 128 x 18 of cell array with the DQ pins numbered DQ0~DQ17.
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K4C89183AF
Absolute Maximum Ratings
Symbol VDD VDDQ VIN VOUT VREF TOPR TSTG TSOLDER PD IOUT Parameter Power Supply Voltage Power Supply Voltage (for I/O buffer) Input Voltage DQ pin Voltage Input Reference Voltage Operating Temperature Storage Temperature Soldering Temperature(10s) Power Dissipation Short Circuit Output Current Rating -0.3 ~ 3.3 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 -0.3 ~ VDDQ + 0.3 -0.3 ~ VDDQ + 0.3 0 ~ 85 -55 ~ 150 260 2 50 Units V V V V V
O
Notes
C C C
Case Temp.
O
O
W mA
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommended DC,AC Operating Conditions (Notes : 1)
Symbol VDD VDDQ VREF VIH (DC) VIL(DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Reference Voltage Input DC high Voltage Input DC Low Voltage Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK Inputs (DC) Input AC High Voltage Input AC Low Voltage Input Differential Voltage. CLK and CLK Inputs (AC) Differential AC Input Cross Point Voltage Differential Clock AC Middle Level Parameter Min 2.375 1.7 VDDQ/2x95% VREF+0.125 -0.1 -0.1 0.4 VREF+0.2 -0.1 0.55 VDDQ/2-0.125 VDDQ/2-0.125 Typ 2.5 1.8
(Tcase = 0 ~ 85 OC) Max 2.625 1.9 VDDQ/2x105% VDDQ+0.2 VREF-0.125 VDDQ+0.1 VDDQ+0.2 VDDQ+0.2 VREF-0.2 VDDQ+0.2 VDDQ/2+0.125 VDDQ/2+0.125 Units V V V V V V V V V V V V 2 5 5 10 7,10 3,6 4,6 7,10 8,10 9,10 Notes
VDDQ/2 -
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K4C89183AF
Notes: 1. All voltages are referenced to Vss, VssQ. 2. VREF is expected to track variations in VddQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed 2% of VREF (DC). 3. Overshoot Iimit : VIH(max.) = VddQ + 0.7V with a pulse width <= 5ns 4. Undershoot Iimit : VIL(min.) = -0.7V with a pulse width <= 5ns 5. VIH(DC) and VIL(DC) are levels to maintain the current logic state. 6. VIH(AC) and VIL(AC) are levels to change to the new logic state. 7. VID is magnitude of the difference between CLK input level and CLK input level. 8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device. 9. VISO means [VICK(CLK) + VICK(CLK)]/2 10. Refer to the figure below.
CLK
VX VX VICK VX VX VICK VICK VX VID(AC)
CLK
VICK
VSS VID(AC) 0 V Differential VISO
VISO(min) VISO(max)
VSS 11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of VREF(DC) 0.04V.
Pin Capacitance (VDD= 2.5V, VDDQ = 1.8V, f = 1 MHz, Ta = 25oC)
Symbol CIN CINC CI/O CNC Input Pin Capacitance Clock Pin (CLK, CLK) Capacitance DQ, DS, QS Capacitance NC Pin Capacitance Parameter Min 1.5 1.5 2.5 Max 3.0 3.0 3.5 1.5 Delts 0.25 0.25 0.5 Units pF pF pF pF
Note : These parameters are periodically sampled and not 100% tested.
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K4C89183AF
DC Characteristics and Operating Conditions
Parameter Operating Current One bank Read or Write operation; tCK = min, IRC = min, IOUT = 0mA; Burst Length = 4, CAS Latency = 6, Free running QS mode; 0V VIN VIL(AC) (max.), VIH(AC)(min.) VIN VDDQ; Address inputs change up to 2 times during minimum IRC, Read data change twice per clock cycle Standby Current All Banks : inactive state; tCK=min, CS = VIH, PD = VIH; 0V VIN VIL(AC)(max.), VIH(AC)(min.) VIH VDDQ; Other input signals change one time during 4*tCK, DQ and DS inputs change twice per clock cycle Standby (Power Down) Current All Banks : inactive state; tCK=min, PD = VIL (Power Down); CAS Latency = 6, Free running QS mode; 0V VIN VIL(AC)(max), VIH(AC)(min) VIN VDDQ; Other input signals change one time during 4*tCK, DQ and DS inputs are floating(VDDQ/2) Write Operating Current(4 Banks) 4 Bank intereaved continuous burst write operation; tCK = min, IRC = min; Burst Length = 4, CAS Latency = 6, Free running QS mode; 0V VIN VIL(AC) (max.), VIH(AC)(min.) VIN VDDQ; Address inputs change once per clock cycle, DQ and DS inputs change twice per clock cycle Read Operating Current(4 Banks) 4 Bank intereaved continuous burst write operation; tCK = min, IRC = min, IOUT = 0mA; Burst Length = 4, CAS Latency = 6, Free running QS mode; 0V VIN VIL(AC) (max.), VIH(AC)(min.) VIN VDDQ; Address inputs change once per clock cycle, Read data change twice per clock cycle Burst Auto-Refresh Current Refresh command at every IREFC interval; tCK = min, IREFC= min; CAS Latency = 6, Free running QS mode; 0V VIN VIL(AC) (max.), VIH(AC) (min.) VIN VDDQ; Address change up to 2 times during minimum IREFC, DQ and DS inputs change twice per clock cycle (VDD = 2.5V 0.125V, VDDQ = 1.8V 0.1V, Tcase = 0~85 C) Symbol Max F6 FB F5 Units Notes
IDD1S
320
300
280
1, 2
IDD2N
100
95
90
1
IDD2P
70
65
60
1
mA
IDD4W
650
600
550
1
IDD4R
650
600
550
1,2
IDD5B
250
235
210
1,3
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K4C89183AF
DC Characteristics and Operating Conditions
Parameter Input Leakage Current (0V<=VIN<=VddQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V<=VOUT<=VddQ) VREF Current Normal Output Driver Strong Output Driver Weak Output Driver Normal Output Driver Strong Output Driver Weak Output Driver Output DC Current (VDDQ = 1.4 ~ 1.6V) Output DC Current (VDDQ = 1.7 ~ 1.9V) VOH = 1.420V VOL = 0.280V VOH = 1.420V VOL = 0.280V VOH = 1.420V VOL = 0.280V VOH = VDDQ - 0.4 VOL = 0.4V VOH = VDDQ - 0.4 VOL = 0.4V Not defined Not defined (VDD = 2.5V 0.125V, VDDQ = 1.8V 0.1V, Tcase = 0~85 C) Symbol ILI ILO IREF IOH(DC) IOL(DC) IOH(DC) IOL(DC) IOH(DC) IOL(DC) IOH(DC) IOL(DC) IOH(DC) IOL(DC) IOH(DC) IOL(DC) Min -5 -5 -5 -5.6 5.6 -9.8 9.8 -2.8 2.8 -4 -4 -8 -8 Max 5 5 5 mA mA 3 3 3 3 4 4 Unit uA uA uA 4 4 4 Notes
Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters depend on the output loading. The specified values are obtained with the output open. 3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to tREFI specification 4. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
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K4C89183AF
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol
tRC
Parameter
Random Cycle Time CL = 4
F6 Min
20.0 4.0 3.33 3.0 0.45*tCK 0.45*tCK -0.45 -0.5 -0.5 min(tCH, tCL)
FB Max
6.0 6.0 6.0 20.0 0.45 0.2 0.5 0.5 -
F5 Max
6.0 6.0 6.0 22.5 0.45 0.25 0.5 0.5 -
Min
22.5 4.5 3.75 3.33 0.45*tCK 0.45*tCK -0.45 -0.5 -0.5 min(tCH, tCL)
Min
25 5.0 4.5 4.0 0.45*tCK 0.45*tCK -0.5 -0.6 -0.6 min(tCH, tCL)
Max
6.0 6.0 6.0 25 0.5 0.3 0.6 0.6 0.055x tCK+0.17 1.2*tCK 0.55*tCK -
Units Notes
3 3 3 3 3 3 3 3, 8 4 3, 8 3, 8 3 4, 8 4, 8
tCK
Clock Cycle Time
CL = 5 CL = 6
tRAC tCH tCL tCKQS tQSQ tAC tOH tHP tQSP tQSQV tQHS tDQSS tDSPRE tDSPRES tDSPREH tDSP
Random Access Time Clock High Time Clock Low Time QS Access Time from CLK Data Output Skew from QS Data Access Time from CLK Data Output Hold Time from CLK CLK half period ( minium of Actual tCH, tCL) QS(Read) Pulse Width Data Output Valid Time from QS DQ, QS Hold skew factor DS(Write) Low to High Setup Time DS(Write) Preamble Pulse Width DS First Input Setup Time DS First Low Input Hold Time DS High or Low Input Pulse Width CL = 4
tHP-tQHS tHP-tQHS
0.8*tCK 0.4*tCK 0 0.3*tCK 0.45*tCK 0.75 0.75 0.75 0.45*tCK CL = 4 0.75 0.75 0.75 0.3 0.3 0.6 0.6
tHP-tQHS tHP-tQHS
0.8*tCK 0.4*tCK 0 0.3*tCK 0.45*tCK 0.8 0.8 0.8 0.45*tCK 0.8 0.8 0.8 0.35 0.35 0.6 0.6
tHP-tQHS tHP-tQHS
0.8*tCK 0.4*tCK 0 0.3*tCK 0.45*tCK 1.0 1.0 1.0 0.45*tCK
0.055x tCK+0.17 1.2*tCK 0.55*tCK -
0.055x tCK+0.17 1.2*tCK 0.55*tCK -
ns
3 4 3 3 4 3, 4 3, 4 3, 4 3, 4 4 3, 4 3, 4 3, 4
tDSS
DS Input Falling Edge to Clock Setup Time
CL = 5 CL = 6 CL = 7
tDSPST
DS(Write) Postamble Pulse Width
-
1.0 1.0 1.0 0.4 0.4 0.7 0.7
tDSPSTH
DS(Write) Postamble Hold Time
CL = 5 CL = 6 CL = 7
-
3, 4 4 4 3 3
tDS tDH tIS tIH
Data Input Setup Time from DS Data Input Hold Time from DS Command / Address Input Setup Time Command / Address Input Hold Time
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K4C89183AF
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
Symbol
tLZ tHZ tQPDH tPDEX tT tFPDL tREFI tPAUSE
Parameter
Data-out Low Impedance Time from CLK Data-out High Impedance Time from CLK Last Output to PD High Hold Time Power Down Exit Time Input Transition Time PD Low Input Window for Self-Refresh Entry Auto-Refresh Average Interval Pause Time after Power-up CL = 4
F6 Min
-0.5 0 0.6 0.1 -0.5*tCK 0.4 200 5 6 7 1 CL = 4 4 5 6 2 BL = 4 3 1 CL = 4 7 7 7
FB Max
0.5 1 5 3.9 1 -
F5 Max
0.5 1 5 3.9 1 -
Min
-0.5 0 0.6 0.1 -0.5*tCK 0.4 200 5 6 7 1 4 5 6 2 3 1 7 7 7
Min
-0.6 0 0.7 0.1 -0.5*tCK 0.4 200 5 6 7 1 4 5 6 2 3 1 7 7 7
Max
0.6 1 5 3.9
Units Notes
3, 6, 8 3, 7, 8
3
3 5 us
1 Cycle
IRC
Random Read/Write Cycle Time (Applicable to Same Bank)
CL = 5 CL = 6 CL = 7
IRCD
RDA/WRA to LAL Command Input Delay (Applicable to Same Bank)
IRAS
LAL to RDA/WRA Command Input Delay (Applicable to Same Bank)
CL = 5 CL = 6 CL = 7
IRBD IRWD IWRD
Random Bank Access Delay (Applicable to Other Bank) LAL following RDA to WRA Delay (Applicable to Other Bank) LAL following WRA to RDA Delay (Applicable to Other Bank)
IRSC
Mode Register Set Cycle Time
CL = 5 CL = 6 CL = 7
IPD IPDA
PD Low to Inactive State of Input Buffer PD High to Active State of Input Buffer CL = 4
1 19 23 25
2 -
1 19 23 25
2 -
1 19 23 25
2 -
IPDV
Power down mode valid from REF command
CL = 5 CL = 6 CL = 7 CL = 4
19 23 25
-
19 23 25
-
19 23 25
-
IREFC
Auto-Refresh Cycle Time
CL = 5 CL = 6 CL = 7
ILOCK
DLL Lock-on Time (Applicable to RDA command)
200
-
200
-
200
-
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K4C89183AF
AC Test Conditions
Symbol VIH(min) VIL (max) VREF VTT VSWING VR VID(AC) SLEW VOTR Parameter Input high voltage (minimum) Input low voltage (maximum) Input reference voltage Termination voltage Input signal peak to peak swing Differential clock input reference level Input differential voltage Input signal minimum slew rate Output timing measurement reference voltage VddQ VTT VIH min(AC) VSWING VREF VIL max(AC) Measurement Point Vss T T 25 Output Value VREF + 0.2 VREF - 0.2 VddQ/2 VREF 0.7 VX(AC) 1.0 2.5 VddQ/2 Units V V V V V V V V/ns V 9 Notes
Slew=(VIHmin(AC) - VILmax(AC))/T
AC Test Load
Notes : 1. Transition times are measured between VIH min(DC) and VIL max(DC). Transition (rise and fall) of input signals have a fixed slope. 2. If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.8*tCK, tCK = 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.) 3. These parameters are measured from the differential clock (CLK and CLK) AC cross point. 4. These parameters are measured from signal transition point of DS crossing VREF level. 5. The tREFI (MAX.) applies to equally distributed refresh method. The tREFI (MIN.) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the maximum. 6. Low Impedance State is speified at VddQ/2 0.2V from steady state. 7. High Impedance State is specified where output buffer is no longer driven. 8. These parameters depend on the clock jitter. These parameters are measured at stable clock. 9. Output timing is measured by using Normal driver strength at VDDQ = 1.7V ~ 1.9V. Output timing is measured by using Strong driver strength at VDDQ = 1.4V ~ 1.6V
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K4C89183AF
Power Up Sequence
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection. 2. Apply VDD before or at the same time as VDDQ. 3. Apply VDDQ before or at the same time as VREF. 4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.). 5. After stable power and clock, apply DESL and take PD = H. 6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1) 7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1) 8. Issue two or more Auto-Refresh commands. (Note:1) 9. Ready for normal operation after 200 clocks from Extended Mode Register programming. Note : 1. Sequence 6, 7 and 8 can be issued in random order. 2. L=Logic Low, H = Logic High
2.5V(TYP)

VDD
1.8V(TYP)

VDDQ
0.9V(TYP)

VREF CLK CLK
200 s(min)

tPDEX IPDA lRSC

lRSC
lREFC

lREFC

PD

200 clock cycle(min)

Command
DESL
RDA MRS
DESL
RDA MRS
DESL WRA REF
DESL
WRA REF
DESL
op-code
op-code

Address
EMRS
MRS

DQ

DS
Hi-Z

QS (Uni-QS mode) QS (Free Running mode)
Low
EMRS

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MRS

Auto Refresh cycle

Normal Operation
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K4C89183AF
Basic Timing Diagrams
Input Timing
Command and Address
tCK tCK tCH tCL
CK
~ ~
CK
tIS tIH 1st tIPW tIS tIH 1st tIS 2nd tIPW tIS tIH UA, BA tIS LA tIH tIH tIS 2nd tIH
~~ ~~
CS
~~ ~~
FN
~~ ~~
A0-A14 BA0.BA1
~ ~
Data
DS
tDS tDH tDS tDH
~~ ~~ ~~ ~~
DQn (Input)
tDS tDH tDS tDH
DQm (Input)
Refer to the Command Truth Table.
Timing of the CLK, CLK
CLK CLK
tCH
tCL VIH VIH(AC) VIL(AC) VIL
tT tCK
tT
CLK CLK
VX VX VX
VIH VID(AC) VIL
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K4C89183AF
Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tCH
tCL
tCK
CK CK Input (Control & Addresses) LDS/UDS (Input)
tCKQS tCKQS tQSP tQSP Low tLZ tQSQ tQSQV tQSQ Q1 tAC tQSQV Q2 tAC Q3 tOH tQSQ tHZ tIS tIH LAL (after RDA) DESL
CAS latency = 4 LQS/UQS (Output)
Low
tCKQS
DQ (Output)
High-Z Q0 tAC
tCKQS
tCKQS tQSP tQSP Low
CAS latency = 5 LQS/UQS (Output)
Low tLZ
tCKQS
tQSQV tQSQ tQSQ Q1 tAC tQSQV Q2 tAC
tQSQ tHZ Q3 tOH
DQ (Output)
High-Z Q0 tAC
tCKQS
tCKQS tQSP tQSP Low
CAS latency = 6 LQS/UQS (Output)
Low tLZ
tCKQS
tQSQV tQSQ tQSQ Q1 tAC tQSQV Q2 tAC
tQSQ tHZ Q3 tOH
DQ (Output)
High-Z Q0 tAC
Note : DQ0 to DQ17 are aligned with LQS. DQ18 to DQ35 are aligned with UQS.
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K4C89183AF
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tCH
tCL
tCK
CK CK Input (Control & Addresses) LDS/UDS (Input)
tCKQS tCKQS tQSP tQSP tIS tIH LAL (after RDA) DESL
CAS latency = 4 LQS/UQS (Output)
tLZ
tCKQS
tQSQV tQSQ tQSQ Q1 tAC tQSQV Q2 tAC
tQSQ tHZ Q3 tOH
DQ (Output)
High-Z Q0 tAC
tCKQS
tCKQS tQSP tQSP
CAS latency = 5 LQS/UQS (Output)
tLZ
tCKQS
tQSQV tQSQ tQSQ Q1 tAC tQSQV Q2 tAC
tQSQ tHZ Q3 tOH
DQ (Output)
High-Z Q0 tAC
tCKQS
tCKQS tQSP tQSP
CAS latency = 6 LQS/UQS (Output)
tLZ
tCKQS
tQSQV tQSQ tQSQ Q1 tAC tQSQV Q2 tAC
tQSQ tHZ Q3 tOH
DQ (Output)
High-Z Q0 tAC
Note : DQ0 to DQ17 are aligned with LQS. DQ18 to DQ35 are aligned with UQS. LQS/UQS is always asserted in Free Running QS mode.
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Write Timing (Burst Length = 4)
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
tCH
tCL
tCK
CK CK Input (Control & Addresses)
tIS tIH LAL (after RDA) DESL tDQSS tDSPRES tDSPSTH tDSS tDSP tDSP tDSP tDSPST
CAS latency = 4 LDS/UDS (Input)
tDSPREH
Preamble tDSPRE tDS tDH
tDSS tDS tDS tDH Q0 Q1 Q2
Postamble
tDH Q3
DQ (Input)
tDQSS tDSPRES tDSS tDSP tDSP tDSP
tDSS tDSPSTH tDSPST
CAS latency = 5 LDS/UDS (Input)
tDSPREH
Preamble
tDSPRE tDS tDS tDH tDH Q1 Q2
Postamble tDS tDH Q3
DQ (Input)
Q0
tDQSS tDSPRES tDSS tDSP tDSP tDSP
tDSS tDSPSTH tDSPST
CAS latency = 6 LDS/UDS (Input)
tDSPREH
Preamble
tDSPRE tDS tDS tDH tDH Q1 Q2
Postamble tDS tDH Q3
DQ (Input)
Q0
LQS/UQS (Uni-QS)
Low
LQS/UQS (Free Runninig) Note : DQ0 to DQ17 are sampled at both edges of LDS. DQ18 to DQ35 are sampled at both edges of UDS.
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tREFI, tPAUSE, Ixxxx Timing
CLK CLK
tIS tIH
tREFI,tPAUSE,IXXXX
~
tIS
tIH
Input (Control & Addresses)
Command
~
Command
Note. "IXXXX"means "IRC", "IRCD", "IRAS", etc.
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Function Truth Table (Notes : 1,2,3)
Command Truth Table (Notes : 4)
*The First Command
Symbol DESL RDA WRA Function Device Deselect Read with Auto-close Write with Auto-close CS H L L FN X H L BA1-BA0 X BA BA A14-A9 X UA UA A8 X UA UA A7 X UA UA A6-A0 X UA UA
*The Second Command (The next clock of RDA or WRA command)
Symbol LAL REF MRS Function Lower Address Latch Auto-Refresh Mode Register Set CS H L L FN X X X BA1-BA0 A14-A13 A12-A11 A10-A9 X X V V X L X X L X X L A8 X X L A7 X X V A6-A0 LA X V
Notes : 1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), BA = Bank Address, UA = Upper Address, LA = Lower Address. 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the command table below.
Read Command Table
Command (Symbol) RDA (1st) LAL (2nd) CS L H FN H X BA1-BA0 BA X A14-A9 UA X A8 UA X A7 UA X A6-A0 UA LA Notes
Write Command Table
Command (Symbol) WRA (1st) LAL (2nd) CS L H FN L X BA1BA0 BA X A14 UA VW0 A13 UA VW1 A12 UA X A11 UA X A10~ A9 UA X A8 UA X A7 UA X A6-A0 UA LA
Notes : 5. A14~A13 are used for Variable Write Length (VW) control at Write Operation.
VW Truth Table
Function Reserved BL = 4 Write All Words Write First Two Words Write First One Word VW0 L H L H VW1 L L H H
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Function Truth Table (Continued)
Mode Register Set Command Truth Table
Command (Symbol) RDA (1st) MRS (2nd) CS L L FN H X BA1-BA0 X V A14-A9 X L A8 X L A7 X V A6-A0 X V 6 Notes
Note : 6. Refer to "Mode Register Table".
Auto-Refresh Command Table
Function Active Auto-Refresh Command (Symbol) WRA(1st) REF(2nd) Current State Standby Active PD CS n-1 H H n H H L L L X X X X X X X X X X X FN BA1-BA0 A14-A9 A8 A7 A6-A0 Notes
Power Down Table
Function Power Down Entry Power Down Continue Power Down Exit Command (Symbol) PDEN PDEX Current State Standby Power Down Power Down PD CS n-1 H L L n L L H H X H X X X FN BA1BA0 X X X A14-A9 X X X A8 X X X A7 X X X A6-A0 Notes X X X 9 8
Notes : 7. PD has to be brought to Low within tFPDL from REF command. 8. PD should be brought to Low after DQ's state turned high impedance. 9. When PD is brought to High from Low, this function is executed asynchronously.
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Function Truth Table (Continued)
Current State PD n-1 H H H H H L H H Row Active for Read H H L H H Row Active for Write H H L H H Read H H H L H H Write H H H L H H Auto-Refreshing H H H L H H Mode Register Accessing H H H L H L L L n H H H L L X H H L L X H H L L X H H H L L X H H H L L X H H H L L X H H H L L X X L H H CS H L L H L X H L H L X H L H L X H L L H L X H L L H L X H L L H L X H L L H L X X X H L FN X H L X X X X X X X X X X X X X X H L X X X X H L X X X X H L X X X X H L X X X X X X X Address X BA, UA BA, UA X X X LA Op-Code X X X LA X X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X X X X Command DESL RDA WRA PDEN LAL MRS/EMRS PDEN MRS/EMRS LAL REF PDEN REF (Self) DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN RDEX NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down state Begin read Access to Mode Register Illegal Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh entry Invalid Continue burst read to end Illegal Illegal Illegal Illegal Invalid Data write & continue burst write to end Illegal Illegal Illegal Illegal Invalid NOP-> Idle after IREFC Illegal Illegal Self-Refresh entry Illegal Refer to Self-Refreshing state Nop-> Idle after IRSC Illegal Illegal Illegal Illegal Invalid Invalid Maintain Power Down Mode Exit Power Down Mode->Idle after tPDEX Illegal 12 11 11 11 11 10 Action Notes
Idle
Power Down
Notes : 10. Illegal if any bank is not idle. 11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA). 12. Illegal if tFPDL is not Stisfied.
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Mode Register Table
Regular Mode Register (Notes : 1)
Address Register BA1*1 0 BA0*1 0 A14-A8 0 A7*3 TM A6-A4 CL A3 BT A2-A0 BL
A7 0 1
Test Mode (TE) Regular (Default) Test Mode Entry
A3 0 1
Burst Type (BT) Sequential Interleave
A6 0 0 0 1 1 1 1
A5 0 1 1 0 0 1 1
A4 X 0 1 0 1 0 1
CAS Latency (CL) Reserved *2 Reserved *2 Reserved *2 4 5 6 Reserved *2
A2 0 0 0 0 1
A1 0 0 1 1 X
A0 0 1 0 1
Burst Length (BL) Reserved *2 Reserved *2 4 Reserved *2
X
Extended Mode Register (Notes : 4)
Address Register BA1*4 0 BA0*4 1 A14-A7 0 A6~A5 SS A4-A3 DIC(QS) A2~A1 DIC(DQ) A0*5 DS
A6 0 0 1 1
A5 0 1 0 1
Strobe Select Reserved
*2
QS A4 0 0 1 1 A3 0 1 0 1 A2 0 0 1 1
DQ A1 0 1 0 1
Output Driver Impedance Control (DIC) Normal Output Driver Strong Output Driver Weak Output Driver Reserved
Reserved*2 Unidirectional DS/QS Unidirectional DS/Free Running QS
Note : 1. Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0. 2. "Reserved" places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to "0"(Low state). Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
A0 0 1
DLL Switch (DS) DLL Enable DLL Disable
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State Diagram
Power Down
PDEX (PD = H) PDEN (PD = L) Standby (Idle)
PD = H AutoRefresh WRA
Mode Register RDA
REF
MRS
Active (Restore)
Active
LAL
LAL
Write (Buffer)
Read
Command Input Automatic Return The second command at Active state must be issued 1clock after RDA or WRA command input
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Timing Diagrams
Single Bank Read Timing (CL=4)
0 CLK CLK lRC=5cycles Command RDA LAL DESL lRAS=4cycles RDA LAL lRC=5cycles DESL lRAS=4cycles RDA LAL lRC=5cycles DESL lRAS=4cycles UA RDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lRCD=1cycle Address UA LA
lRCD=1cycle UA LA
lRCD=1cycle UA LA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode DS (Input)
QS (Output)
Low CL=4 CL=4 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 CL=4 Q0
DQ (Output)
Hi-Z
Unidirectional DS/Free Running QS mode
DS (Input)
QS (Output) CL=4 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 CL=4 CL=4 Q0
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Single Bank Read Timing (CL=5)
0 CLK CLK lRC=6cycles Command RDA LAL DESL lRAS=5cycles RDA LAL lRC=6cycles DESL lRAS=5cycles RDA lRCD=1cycle UA LA LAL DESL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lRCD=1cycle Address UA LA
lRCD=1cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
DS (Input)
QS (Output)
Low CL=5 CL=5 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3
DQ (Output)
Hi-Z
Unidirectional DS/Free Running QS mode DS (Input)
QS (Output) CL=5 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 CL=5 Q0 Q1 Q2 Q3
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Single Bank Read Timing (CL=6)
0 CLK CLK lRC=7cycles Command RDA LAL DESL lRAS=6cycles RDA LAL lRC=7cycles DESL lRAS=6cycles RDA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lRCD=1cycle Address UA LA
lRCD=1cycle UA LA
lRCD=1cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
DS (Input)
QS (Output)
Low CL=6 CL=6 Q0 Q1 Q2 Q3 Q0 Q1 Q2
DQ (Output)
Hi-Z
Unidirectional DS/Free Running QS mode
DS (Input)
QS (Output) CL=6 DQ (Output) Hi-Z Q0 Q1 Q2 Q3 CL=6 Q0 Q1 Q2
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Single Bank Write Timing (CL=4)
0 CLK CLK lRC=5cycles Command WRA LAL DESL lRAS=4cycles WRA LAL lRC=5cycles DESL lRAS=4cycles WRA LAL lRC=5cycles DESL lRAS=4cycles UA WRA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lRCD=1cycle Address UA LA
lRCD=1cycle UA LA
lRCD=1cycle UA LA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode DS (Input)
QS (Output)
Low WL=3 WL=3 D0 D1 D2 D3 D0 D1 D2 D3 WL=3 D0 D1 D2 D3
DQ (Input)
Unidirectional DS/Free Running QS mode DS (Input)
QS (Output) WL=3 DQ (Input) D0 D1 D2 D3 WL=3 D0 D1 D2 D3 WL=3 D0 D1 D2 D3
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Single Bank Write Timing (CL=5)
0 CLK CLK lRC=6cycles Command WRA LAL DESL lRAS=5cycles WRA LAL lRC=6cycles DESL lRAS=5cycles WRA LAL DESL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lRCD=1cycle Address UA LA
lRCD=1cycle UA LA
lRCD=1cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
DS (Input)
QS (Output)
Low WL=4 WL=4 D0 D1 D2 D3 D0 D1 D2 D3
DQ (Input)
Unidirectional DS/Free Running QS mode DS (Input)
QS (Output) WL=4 DQ (Input) D0 D1 D2 D3 WL=4 D0 D1 D2 D3
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Single Bank Write Timing (CL=6)
0 CLK CLK lRC=7cycles Command WRA LAL DESL lRAS=6cycles WRA LAL lRC=7cycles DESL lRAS=6cycles WRA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lRCD=1cycle Address UA LA
lRCD=1cycle UA LA
lRCD=1cycle UA LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode DS (Input)
QS (Output)
Low WL=5 WL=5 D0 D1 D2 D3 D0 D1 D2 D3
DQ (Input)
Unidirectional DS/Free Running QS mode DS (Input)
QS (Output) WL=5 DQ (Input) D0 D1 D2 D3 WL=5 D0 D1 D2 D3
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Single Bank Read-Write Timing (CL=4)
0 CLK CLK lRC=5cycles Command RDA LAL DESL WRA LAL lRC=5cycles DESL RDA LAL lRC=5cycles DESL WRA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA
LA
UA
LA
UA
LA
UA
Bank Add.
#0
#0
#0
#0
Unidirectional DS/QS mode
DS (input)
QS (Output)
Low CL=4 WL=3 Q0 Q1 Q2 Q3 D0 D1 D2 D3 CL=4 Q0
DQ
Hi-Z
Unidirectional DS/Free Running QS mode DS (input)
QS (Output) CL=4 DQ Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 WL=3 CL=4
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Single Bank Read-Write Timing (CL=5)
0 CLK CLK lRC=6cycles Command RDA LAL DESL WRA LAL lRC=6cycles DESL RDA LAL DESL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode DS (input)
QS (Output)
Low CL=5 WL=4 Q0 Q1 Q2 Q3 D0 D1 D2 D3
DQ
Hi-Z
Unidirectional DS/Free Running QS mode DS (input)
QS (Output) CL=5 DQ Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 WL=4
Read data
Write data
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Single Bank Read-Write Timing (CL=6)
0 CLK CLK lRC=7cycles Command RDA LAL DESL WRA LAL lRC=7cycles DESL RDA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA
LA
UA
LA
UA
LA
Bank Add.
#0
#0
#0
Unidirectional DS/QS mode
DS (input)
QS (Output)
Low CL=6 WL=5 Q0 Q1 Q2 Q3 D0 D1 D2 D3
DQ
Hi-Z
Unidirectional DS/Free Running QS mode
DS (input)
QS (Output) CL=6 DQ Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 WL=5
Read data
Write data
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Multiple Bank Read Timing (CL=4)
0 CLK CLK lRBD=2cycles Command RDA LAL RDA LAL DESL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA LAL RDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "c"
LA
UA Bank "d"
LA
UA Bank "a"
LA
UA Bank "b"
Bank Add.
lRC(Bank"a")=5cycles Unidirectional DS/QS mode lRC(Bank"b")=5cycles
DS (input) QS (Output) Low CL=4 CL=4 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2
Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=4 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2
CL=4
Note : lRC to the same bank must be satisfied
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Multiple Bank Read Timing (CL=5)
0 CLK CLK lRBD=2cycles Command RDA LAL RDA LAL DESL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "c"
LA
UA Bank "d"
LA
UA Bank "a"
LA
Bank Add.
lRC(Bank"a")=6cycles Unidirectional DS/QS mode lRC(Bank"6")=6cycles
DS (input) QS (Output) Low CL=5 CL=5 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=5 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2
CL=5
Note : lRC to the same bank must be satisfied
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Multiple Bank Read Timing (CL=6)
0 CLK CLK lRBD=2cycles Command RDA LAL RDA LAL DESL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA lRBD=2cycles LAL RDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "c"
LA
UA Bank "d"
LA
UA Bank "a"
Bank Add.
lRC(Bank"a")=7cycles Unidirectional DS/QS mode lRC(Bank"b")=7cycles
DS (input) QS (Output) Low CL=6 CL=6 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2
Unidirectional DS/Free Running QS mode DS (input) QS (Output) CL=6 DQ (Output) Hi-Z Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qa2
CL=6
Note : lRC to the same bank must be satisfied
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Multiple Bank Write Timing (CL=4)
0 CLK CLK lRBD=2cycles Command WRA LAL WRA LAL DESL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA LAL WRA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "c"
LA
UA Bank "d"
LA
UA Bank "a"
LA
UA Bank "b"
Bank Add.
lRC(Bank"a")=5cycles Unidirectional DS/QS mode lRC(Bank"b")=5cycles
DS (input) QS (Output) Low WL=3 WL=3 DQ (Input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
Unidirectional DS/Free Running QS mode DS (input) QS (Output) WL=3 DQ (Input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1
WL=3
Note : lRC to the same bank must be satisfied
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Multiple Bank Write Timing (CL=5)
0 CLK CLK lRBD=2cycles Command WRA LAL WRA LAL DESL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA LAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "c"
LA
UA Bank "d"
LA
UA Bank "a"
LA
Bank Add.
lRC(Bank"a")=6cycles Unidirectional DS/QS mode DS (input) QS (Output) Low WL=4 WL=4 DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1 lRC(Bank"b")=6cycles
Unidirectional DS/Free Running QS mode DS (input) QS (Output) WL=4 DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Dc0 Dc1
WL=4
Note :IRC to the same bank must be satisfied.
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Multiple Bank Write Timing (CL=6)
0 CLK CLK lRBD=2cycles Command WRA LAL WRA LAL DESL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA lRBD=2cycles LAL WRA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "a"
LA
UA Bank "b"
LA
UA Bank "c"
LA
UA Bank "d"
LA
UA Bank "a"
Bank Add.
lRC(Bank"a")=7cycles Unidirectional DS/QS mode DS (input) QS (Output) Low WL=5 WL=5 DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1 lRC(Bank"a")=7cycles
Unidirectional DS/Free Running QS mode DS (input) QS (Output) WL=5 DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 Da0 Da1 Da2 Da3 Db0 Db1
WL=5
Note :IRC to the same bank must be satisfied.
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Multiple Bank Read-Write Timing (BL=4)
0 CLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lRBD=2cycles Command WRA LAL RDA LAL DESL lRWD=3cycles LA UA Bank "c" lRC(Bank"a") lRC(Bank"a") WRA LAL RDA LAL DESL lRWD=3cycles LA UA Bank "a" WRA LAL RDA LAL
lWRD=1cycle Address Bank Add. UA Bank "a" LA UA Bank "b"
lWRD=1cycle LA UA Bank "d"
lWRD=1cycle LA UA Bank "b" LA
Unidirectional DS/QS mode CL =4 DS (Input) Low WL=3 DQ (Output) Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 CL=4
QS (Output)
CL =5
DS (Input) Low WL=4 CL=5 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3
QS (Output) DQ (Output)
Hi-Z
CL =6
DS (Input)
QS (Output) DQ (Output)
Low WL=5 Hi-Z Da0 Da1 Da2 Da3 Note :IRC to the same bank must be satisfied. Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 CL=6
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Multiple Bank Read-Write Timing (BL=4)
0 CLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
lRBD=2cycles Command WRA LAL RDA LAL DESL lRWD=3cycles LA UA Bank "c" WRA LAL RDA LAL DESL lRWD=3cycles LA UA Bank "a" WRA LAL RDA LAL
lWRD=1cycle Address Bank Add. UA Bank "a" LA UA Bank "b"
lWRD=1cycle LA UA Bank "d"
lWRD=1cycle LA UA Bank "b" LA
lRC(Bank"a") lRC(Bank"a")
Unidirectional DS/Free Running QS mode CL =4 DS (Input)
QS (Output) WL=3 DQ (Output) Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 CL=4
CL =5
DS (Input)
QS (Output) WL=4 DQ (Output) Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 CL=5
CL =6
DS (Input)
QS (Output) WL=5 DQ (Output) Hi-Z Da0 Da1 Da2 Da3 Note :IRC to the same bank must be satisfied. Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da2 Da3 Qb0 Qb1 CL=6
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K4C89183AF
Write with Variable Write Length (VW) Control(CL=4)
0 CLK CLK BL=2, SEQUENTIAL MODE Command WRA LAL DESL WRA LAL DESL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
UA
LA=#3 VW=All
UA
LA=#1 VW=1
VW0 = Low VW1 = don't care Bank Add. Bank "a" Bank "a"
VW0 = High VW1 = don't care
DS (Input)
DQ (Input)
D0 D1 Lower Address #3 #2
D0 #1 (#0) Last one data is masked.
BL=4, SEQUENTIAL MODE Command WRA LAL DESL WRA LAL DESL WRA LAL DESL
Address
UA
LA=#3 VW=All
UA
LA=#1 VW=1
UA
LA=#2 VW=2
VW0 = High VW1 = Low Bank Add. Bank "a" Bank "a"
VW0 = High VW1 = High Bank "a"
VW0 = Low VW1 = High
DS (Input)
DQ (Input)
D0 D1 D2 D3 Lower Address #3 #0 #1 #2
D0 #1 (#2) (#3) (#0) Last three data are masked.
D0 D1 #2 #3 (#0) (#1)
Last two data are masked.
Note : DS input must be continued till end of burst count even if some of laster data is masked.
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K4C89183AF
Power Down Timing (CL=4, BL=4)
Read cycle to Power Down Mode
0 CLK CLK BL=2, SEQUENTIAL MODE Command RDA LAL DESL 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3

DESL IPDA
RDA or WRA
Address
UA
LA tIH tIS IPD=2 cycle
UA
PD tQPDH Unidirectional DS/QS mode DS (input)
IRC(min), tREFI(max)

tPDEX
QS (Output)
Low CL=4

DQ (Output)
Hi-Z Q0 Q1 Q2 Q3
Hi-Z
Unidirectional DS/Free Running QS mode

DS (input)
QS (Output) CL=4 DC (Output) Hi-Z Q0 Q1 Q2 Q3
Hi-Z
Power Down Entry Note : PD must be kept "High" level until end of Burst data output. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" and a stable clock signal must be maintained. When PD is brought to "High", a valid executable command may be applied IPDA cycles later.
Power Down Exit
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K4C89183AF
Power Down Timing (CL=4, BL=4)
Write cycle to Power Down Mode
0 CLK CLK 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3

IPDA DESL
RDA or WRA
Command
WRA
LAL
DESL
Address
UA
LA tIH tIS IPD=2 cycle
UA
PD

tPDEX
WL=3 Unidirectional DS/QS mode DS (input)
IPD=2 cycle IRC(min), tREFI(max)

QS (Output)
Low WL=3

DC (Output)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode

DS (input)
QS (Output) WL=3 DC (Output) D0 D1 D2 D3
Note : PD must be kept "High" level until end of Burst data output. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" and a stable clock signal must be maintained. When PD is brought to "High", a valid executable command may be applied IPDA cycles later.
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K4C89183AF
Mode Register Set Timing (CL=4, BL=4)
From Write operation to Mode Register Set operation
0 CLK CLK lRC=7cycles Command WRA LAL DESL RDA MRS DESL
RDA or WRA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LAL
A14~A0
UA
LA
Valid (opcode)
UA
LA
BA0, BA1
BA WL + BL/2
BA0="0" BA1="0"
BA
Unidirectional DS/QS mode DS (input)
QS (Output)
Low
DC (input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS (input)
QS (Output)
DC (input)
D0 D1 D2 D3
Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
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K4C89183AF
Extended Mode Register Set Timing (CL=4, BL=4)
From Write operation to Extended Mode Register Set operation
0 CLK CLK lRC=7cycles Command WRA LAL DESL RDA MRS DESL
RDA or WRA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LAL
A14~A0
UA
LA
Valid (opcode)
UA
LA
BA0, BA1
BA WL + BL/2
BA0="0" BA1="0"
BA
Unidirectional DS/QS mode DS (input)
QS (Output)
Low
DQ DC (input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS (input)
QS (Output)
DQ (input)
D0 D1 D2 D3
Note : When DQ strobe mode is changed by EMRS, QS output is invalid for IRSC period. DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
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K4C89183AF
Auto-Refresh Timing (CL=4, BL=4)
Unidirectional DS/QS mode
0 1 2 3 4 5 6 7 n-1 n n+1 n+2
CLK CLK lRC=5cycles Command RDA LAL DESL WRA REF lREFC=19cycles

DESL
RDA or WRA
LAL or MRS or REF
Bank, Address
Bank, UA
LA lRAS=4cycles lRCD=1cycle
lRCD=1cycle QS (output) Low
Low
CL=4 DQ (output) Hi-Z Q0 Q1 Q2 Q3
Hi-Z
Unidirectional DS/Free Running QS mode CLK CLK lRC=5cycles Command RDA LAL DESL WRA REF lREFC=19cycles

DESL
RDA or WRA
LAL or MRS or REF
Bank, Address
Bank, UA
LA lRAS=4cycles lRCD=1cycles
lRCD=1cycles QS (output)
CL=4 DQ (output) Hi-Z Q0 Q1 Q2 Q3
Hi-Z
Note : In case of CL=4, IREFC must be meet 19 clock cycles. When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command specified by tREFI must be satisfied. tREFI is average interval time in 8 Refresh cycles that is sampled randomly.
t1
t2
t3
t7
t8

CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle tREFI = Total time of 8 Refresh cycle = t1+t2+t3+t4+t5+t6+t7+t8 8 8 tREFI is specified to avoid partly concentrated current of Refresh operation that is acivated larger are than Read/Write operation.
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K4C89183AF
Function Description
Network - DRAM
Network - DRAM is an acronym of Double Data Rate Network - DRAM. Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer.
Pin Functions
Clock Inputs : CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS, FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK. The QS and DQ output data are aligned to the crossing point of CLK and CLK. The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
Power Down : PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed.
Chip Select & Function Control : CS & FN
The CS and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs.
Bank Addresses : BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS). BA0 Bank #0 Bank #1 Bank #2 Bank #3 0 1 0 1 BA1 0 0 1 1
Address Inputs : A0 to A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle.
Upper Address K4C89183AF A0 to A14
Lower Address A0 to A6
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K4C89183AF
Functional Description (Continued)
Data Input/Output : DQ0 ~ DQ17
The input data of DQ0 to DQ17 are taken in synchronizing with the both edges of DS input signal. The output data of DQ0 to DQ17 are outputted synchronizing with the both edges of QS output signal.
Data Strobe : DS or QS
Method of data strobe is chosen by Extended mode register. (1) Unidirectional DS/QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. During Write. Auto-Refresh and NOP cycle, QS assert always "Low" level. QS is Hi-Z in Self-Refresh mode. (2) Unidirectional DS/Free running QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe type is easy to use for pin to pin connect application.
Power Supply : VDD, VDDQ, VSS, VSSQ
VDD and VSS are supply pins for memory core and peripheral circuits. VDDQ and VSSQ are power supply pins for the output buffer.
Reference Voltage : VREF
VREF is reference voltage for all input signals.
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K4C89183AF
Command Functions and Operations
K4C89093AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears after CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state after IRC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DS have to be provided for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after IRC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
K4C89093AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by IREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum.
Power Down Mode( PD="L" )
When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89183AF become Power Down Mode by asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD, CLK, CLK and QS. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued for IPDA cycle after PD goes high. The Power Down exit function is asynchronous operation.
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The K4C89183AF have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields.
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K4C89183AF
The four fields are as follows : (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) CAS Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has two function fields. The two fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. (E-3) Data Strobe Select Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation.
* Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1 0 0 1
BA0 0 1 X
A14~A0 Regular MRS cycle Extended MRS cycle Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 4 words. A2 0 0 0 0 1 A1 0 0 1 1 X A0 0 1 0 1 X Burst Length Reserved Reserved 4 words Reserved Reserved
(R-2) Burst Type field (A3) This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words. A3 0 1 Burst Type Sequential Interleave
* Addressing sequence of Sequential mode (A3) A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device.
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K4C89183AF
CAS Latency = 4 (Free Running QS mode)
CK CK Command QS RDA LAL
DQ
Data 0 Data 1 Data 2 Data 3
Addressing sequence for Sequential mode Data Data 0 Data 1 Data 2 Data 3 Access Address n n+1 n+2 n+3 4 words(Address bits is LA1, LA0) not carried from LA1~LA2 Burst Length
Functional Description (Continued)
* Addressing sequence of Inteleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. Addressing sequence for Interleave mode Data Data 0 Data 1 Data 2 Data 3 Access Address ...A8 A7 A6 A5 A4 A3 A2 A1 A0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 4 words Burst Length
(R-3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of clock which should input write data is CAS Latency cycles - 1. Addressing sequence for Interleave mode A6
0 0 0 0 1 1 1 1
A5
0 0 1 1 0 0 1 1
A4
0 1 0 1 0 1 0 1
CAS Latency
Reserved Reserved Reserved Reserved 4 5 6 7
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K4C89183AF
(R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation. (R-5) Reserved field in the Regular Mode Register * Reserved bits (A8 to A14) These bits are reserved for future operations. They must be set to "0" for normal operation.
Extended Mode Register Fields
(E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled. (E-2) Output Driver Impedance Control field (A1 to A4) This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength. QS A4 0 0 1 1 A3 0 1 0 1 A2 0 0 1 1 DQ A1 0 1 0 1 Output Driver Impedance Control Normal Output Driver Strong Output Driver Weaker Output Driver Reserved
(E-3) Strobe Select (A6/A5) Two types of strobe are supported. This field is used to choose the type of data strobe. (1) Unidirectional DS/QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data at Read operation. (2) Unidirectional DS/Free running QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data and always clocking A6 0 0 1 1 A5 0 1 0 1 Strobe Select Reserved Reserved Unidirectional DS/QS mode Unidirectional DS/Free running QS mode
(E-4)Reserved fied (A7 to A14) These bits are reserved for future operations and must be set to "0" for normal operation.
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K4C89183AF
Package Outline Drawing (FBGA 60ball, 1.0 x 1.0 mm)
10.50 0.10 #A1 0.10 Max 1.00 x 5 = 5.00 #A1 Mark (Option) 2.50 1.50 Window Mold Area 6 5 4 3 2 1.50 1.00 1
10.50 0.10
B C
E F
15.50 0.10 15.50 0.10
7.00 1.00 x 14 = 14.00 7.00
D
0.5 0.05
H J K L M N P R
60 - 0.45 solder ball
0.35 0.05
TOP VIEW
1.10 0.10
BOTTOM VIEW
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15.50 0.10
1.00
G
1.00
A
K4C89183AF
General Information
Organization 288M(x9) 288M(x18) 288M(x36) F6 (667Mbps@CL6) K4C89093AF-ACF6 K4C89183AF-ACF6 K4C89363AF-GCF6 FB (600Mbps@CL6 ) K4C89093AF-ACFB K4C89183AF-ACFB K4C89363AF-GCFB F5 (500Mbps@CL6 ) K4C89093AF-AC(I)F5 K4C89183AF-AC(I)F5 K4C89363AF-GC(I)F5
1
2
3
4
5
6
7
8
9
10
11
K 4 C XX XX X X X - X X XX
Memory DRAM Temperature & Power Small Classification Density and Refresh Organization Bank 1. SAMSUNG Memory : K 2. DRAM : 4 3. Small Classification C : Network-DRAM 4. Density & Refresh 89 : 288M 8K/32ms 5. Organization 08 09 16 18 : x8 : x9 : x16 : x18 8. Version F : 7th Generation 9. Package A : 60 FBGA G : 144 FBGA 10. Temperature & Power C : (Commercial, Normal) I : (Industrial, Normal) 11. Speed F6 : 667Mbps/pin (333MHz, CL=6) FB : 600Mbps /pin (300MHz, CL=6) F5 : 500Mbps/pin (250MHz, CL=6) Package Version Interface (VDD & VDDQ) Speed
6. Bank 3 : 4 Bank 7. Interface (VDD & VDDQ) A: SSTL-2(2.5V, 1.8V)
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